1. Field of the Invention
The present invention relates to a Phase Locked Loop (PLL) frequency synthesizer circuit which operates to maintain the frequency of the synthesizer's output signal at a desired frequency value pre-set by a user, and more particularly to a charge-pump circuit which is one of the components of the PLL synthesizing circuit.
2. Description of the Related Art
Recently, PLL frequency synthesizer circuits have found widespread application in such mobile communication devices such as the cellular or cordless phones. The number of these devices used by the public has increased dramatically due to their widespread popularity with the public. With an increased number of the users, it has become necessary to reduce the area of the phone's effective operation and/or to execute a time-division process that ensures the effective time-based usage of a particular frequency used with a particular signal. Digital signal processing has, in response to these constraints, made significant inroads in the technological advancement of mobile communication devices. With the increased use of digital movable communication devices, there is an also a demand to increase the tuning speed of PLL frequency synthesizer circuits. To effect this increase in the tuning speed of the PLL frequency synthesizer, therefore, various techniques have been proposed, the most important of which has been to enhance the characteristics of the charge pump circuit used in the mobile communication device.
FIG. 1 shows a conventional PLL frequency synthesizer circuit 100. The synthesizer circuit 100 is composed of a reference counter 111, a crystal oscillator 112, a comparative frequency divider 113, a phase comparator 117, a charge-pump circuit 118, a low-pass filter (simply referred to as LPF) 119, and a voltage controlled oscillator (simply referred to as VCO) 120. The LPF 119 is composed of an integrating circuit having two resistors R15, R16 and a capacitor C2.
The reference counter 111 operates to divide the frequency of an oscillation signal FOSC, output from the crystal oscillator 112 at a predetermined frequency in order to generate a reference signal FR at a reference frequency. The reference signal FR is output to the phase comparator 117.
The comparative frequency divider 113 includes a prescaler 114, a program counter 115, and a swallow counter 116 for switching a dividing ratio of the prescaler 114. The prescaler 114 divides a frequency of the signal FVCO output from the VCO 120 to generate a frequency-divided signal S1. If the frequency-dividing ratio is expressed by "M", the prescaler 114 normally divides a frequency of the output signal FVCO by a factor of (M+1). Based on a switching signal MC output from the swallow counter 116, the prescaler 114 divides the frequency of the output signal FVCO by a factor of M.
The program counter 115 divides a frequency of the dividing signal S1 to generate a comparison signal FP. The program counter 115 may set the frequency of the comparison signal FP to any value, and divide a frequency of the signal S1 to form a desired frequency. If the frequency-dividing ratio is expressed by ".alpha.", the swallow counter 116 divides a frequency of the signal S1 into a factor of .alpha.. when the frequency-dividing is completed, the swallow counter 116 operates to output a switching signal MC to the prescaler 114.
The phase comparator 117 compares a phase of the reference signal FR with that of the comparison signal FP, and outputs pulsewise phase difference signals .phi.R and .phi.P to the charge-pump circuit 118, based on the phase difference between the signals FR and FP. When the phase difference signal .phi.R is low, the phase difference signal .phi.P is maintained low. When the phase difference signal .phi.P is high, the phase difference signal .phi.R is maintained high.
The charge-pump circuit 118 is provided with a PNP transistor T11, an NPN transistor T12, and four resistors R11 to R14. Each of the transistors T11 and T12 is a bipolar transistor with a grounded emitter. The transistor T11 has its emitter coupled to the power supply Vcc, its collector connected to the LPF 119, and its base connected to the phase comparator 117 via the resistor R12. The base serves to receive the phase difference signal .phi.R and is connected to the power supply VCC via the resistor R11. The transistor T12 has an emitter connected to the ground GND, a collector connected to the LPF 119, a base connected to the phase comparator 117 via the resistor R14. The base serves to receive the phase difference signal .phi.P and is connected to the ground GND via the resistor R13.
When the phase difference signals .phi.R and .phi.P are both maintained at low voltage levels, only the transistor T11 remains on, effectively allowing transistor T11 to control the output of voltage signal DO from transistor T11 to the LPF 119. When the phase difference signals .phi.R and .phi.P are both held at the H level, only the transistor T12 remains on, effectively allowing transistor T12 to control the output of voltage signal DO to the LPF 119. Based on the level of the phase difference signals .phi.R and .phi.P, either the transistors T11 or T12 will be on to change the voltage level of the voltage signal DO. With the transistor T11 on, the voltage level of the voltage signal DO increases and the LPF 119 gets charged by the power supply VCC via the transistor T11. With the transistor T12 on, the voltage level of the voltage signal DO decreases and the LPF 119 discharges to ground GND via the transistor T12.
The LPF 119 operates to smooth the voltage signal DO of the charge-pump circuit 118 by removing high-frequency pulse components. As a result, the LPF 119 outputs a control voltage signal VT having no high-frequency pulse components. The VCO 120 outputs a signal FVCO whose frequency is maintained in correspondence with the value of the control voltage signal VT. The output signal FVCO is fed back to the prescaler 114 of the comparison frequency divider 113.
By the aforementioned signal feedback process, the frequency of the signal FVCO output from the VCO 120 is locked up at a multiple value of the reference signal's frequency.
To increase the tuning speed of the PLL frequency synthesizer circuit as described above, the charge-pump circuit 118 needs to relay the driving current to the LPF 119 in order that the LPF 119 can rapidly charge or discharge. To meet this requirement, when the PNP transistor T11 or the NPN transistor T12 is turned on, the charge-pump circuit 118 has to output larger driving current.
Since the PNP transistor T11 and the NPN transistor T12 are formed on one semiconductor substrate, however, the current amplification of the PNP transistor T11 is inevitably lower than that of the NPN transistor T12. This makes it difficult to improve the performance of the PNP transistor T11. In addition, generally, the current value through the bipolar transistor is constrained by the value of the current's amplification. In conventional charge pumps, therefore, the driving current of the PNP transistor T11 was constrained within a particular range, limiting the charging or discharging speed of the charge-pump circuit 118.
In order to solve the above described problem, a charge-pump circuit 121 shown in FIG. 2 has been proposed for the conventional PLL frequency synthesizer circuit. The charge-pump circuit 121 includes a PMOS transistor 122 and an NMOS transistor 123. The transistor 122 includes a source connected to the power supply VCC, a drain connected to the LPF 119, and a gate for receiving the phase difference signal .phi.R. The transistor 123 has a source connected to the ground GND, a drain connected to the LPF 119, and a gate for receiving the phase difference signal .phi.P.
In the charge-pump circuit 121, when the phase difference signals .phi.R and .phi.P are both held low, only the transistor 122 is turned on, whereas when the phase difference signals .phi.R and .phi.P are both held high, only the transistor 123 is turned on. When the transistor 122 is turned on, the voltage level of the voltage signal DO increases, charging the LPF 119 by the power supply VCC via the transistor 122. When the transistor 123 is turned on, the voltage level of the voltage signal DO decreases, discharging the LPF 119 to the ground GND via the transistor 123.
The magnitude of the driving current flowing through the PMOS or NMOS transistor 122 or 123 is determined based on the resistance of the transistor 122 or 123 when turned on (simply referred to as "on resistance"). Hence, the magnitude of the driving current of the transistor 122 or 123 is larger than that of the bipolar transistor T11 or T12. As a result, the charging or discharging speed of the charge-pump circuit 121 increases, which in turn, allows for the high speed tuning operation of the PLL frequency synthesizer.
If, however, there is a significant change in the on resistance of the transistor 122 or 123, the change has a great effect on the noise characteristics of the PLL frequency synthesizer circuit. Specifically, such large changes in resistance effect the time needed to acquire a lock on the frequency of the output signal FVCO. The on resistance of the transistor 122 or 123 may change quadric-functionally with respect to the change of voltage applied between the source and the drain, and increase as the applied voltage is raised. The voltage between the source and the drain of the transistor 122 or 123 tends to be proportional to the frequency of the output signal FVCO, corresponding to the channel used in the mobile communication devices. Thus, concomitant with increased changes to a channel's locked frequency are increased changes to the on resistance of the transistor 122 or 123. Consequently, the noise characteristics of a PLL frequency synthesizer and the time consumed for locking up a channel (i.e., lock-up time) depends on the change of the channel.